1. Field of the Invention
The present invention relates to an analog to digital conversion circuit (hereinafter referred to as A/D converter), and more particularly to an A/D converter for correcting a direct current offset of a comparative reference voltage of a comparator. In addition, the present invention is used in a field in which a high-speed and high-definition A/D conversion is required in, for example, a parallel-type A/D converter.
2. Description of the Related Art
Conventionally, various types of A/D converters for converting an analog signal to a digital signal are used depending on the resolution and the operation speed thereof. For example, in the case where the resolution is given on a relatively low level on the order of 8 bits or less, and the conversion rate is given on a relatively high level of hundreds of MHz (sample/sec) to several GHz (sample/sec), a parallel type A/D converter is preferable which is simple in structure and which can be easily heightened in speed.
The parallel-type A/D converter which has the simplest structure is a flash-type A/D converter for comparing in a lump the analog input voltage with a plurality of reference voltages.
The flash-type A/D converter includes comparators in the number of resolution portions, a resistor string for generating reference voltages, and an encoder for encoding comparative outputs of the comparators. Analog signals which have been input are input in parallel to all the comparators, and the analog signals are compared with reference voltages at each of the comparators, and as a result, a signal obtained by encoding the comparison result by the encoder is output as an A/D conversion result.
When, in the aforementioned flash-type A/D converter, a direct current offset voltage is generated in the threshold voltage of the comparator due to a mismatch of the element properties, the conversion precision is directly affected. As a method for solving this problem, a method is considered which adds to the A/D converter a digital circuit for correcting the offset voltage to perform calibration. In this method, one of the problems is how the offset correction is realized in a circuit.
Jpn. Pat. Appln. KOKAI Publication No. 6-276098 discloses a technique for dividing a resistor string to generate reference voltages for offset correction in order to perform offset correction of a comparator. That is, an A/D converter comprises a resistor string, a selector, a comparator, an encoder, and a memory. The resistor string is configured so that a plurality of voltages can be taken out which are divided to a number not less than the resolution of the A/D converter. More specifically, resistor elements not less than the resolution are connected in series, and divided voltage is taken out from each of the connection points. Then, an appropriate value of divided voltage is selected by the selector, so that the offset of the comparator is corrected. A control signal of the selector is held in the memory.
With such a configuration, even if an offset occurs in the comparator, the offset is corrected and the precision of the A/D converter can be improved. However, the problem in such a configuration is that the circuit scale of the resistor string, the number of selectors, and the number of control signals of the selectors are increased in proportion to an increase in the number of the steps of correcting the offset voltage.
As has been described above, it is required to provide means for correcting the offset voltage of the comparator in the A/D converter for obtaining a desired conversion precision by means of calibration and trimming. Conventionally, there is a problem in that a larger number of reference voltages are used which number is larger than the desired resolution, and the offset voltage of the comparator is corrected with the result that the circuit scale is increased.
Furthermore, Jpn. Pat. Appln. KOKAI Publication No. 10-65542 discloses a comparator having a function of correcting an offset. In tile comparator disclosed in the above publication, a pair of PMOS transistors is used as a load circuit of two NMOS transistors which are input elements and constitute a differential pair. When an appropriate control signal is given to gate electrodes of the pair of PMOS transistors, the input and output properties of the comparators are changed in accordance with the appropriate signal and a threshold voltage of the comparator is changed, so that the offset of the comparator can be corrected.
However, a relation between a method of controlling a gate signal of the PMOS transistors and the threshold voltage of the comparator depends on the properties of the PMOS transistor serving as a load circuit and the properties of the NMOS transistor serving as an input element. Therefore, there is a problem in that a circuit design of the comparator is difficult, or the change properties of the threshold voltage of the comparator can be easily changed with the operation environment of temperatures, bias conditions or the like.